A Sigma-Delta N-Fractional PLL and Low Phase Noise VCO for Ultra Low-Power Chip-Scale Atomic Clocks
Radojkovic, V.¹; Shi, X.¹; Tanner, S.¹; Farine, P.-A.¹; Rochat, P.^2
1University of Neuchatel; ²SpectraTime

Atomic clocks provide the best long term frequency stability and are required in many modern communication applications such as network synchronisation, channel selectivity, anti-jamming capabilities. They are also of fundamental importance for Global Navigation Satellite Systems (GNSS). For decades, the atomic clock has been a bulky, power consuming and expensive system, which strongly limited its deployment. Its reduction in size and power consumption has therefore been a very active research field, leading to reasonable size (125 cm3) and power consumption (10 W) for the last generation of commercial clocks. Recently, using innovative micro-fabrication techniques, chip-scale atomic clocks with a volume of less than 1 cm3 and a power consumption of a few tens of mW only have been demonstrated. In such systems, the frequency synthesis electronics is a critical component whose performance, along with the atomic cavity, determines the overall stability and power consumption of the system.

This paper reports our progress in developing a prototype of an ultra-stable, high accuracy frequency synthesizer used to generate the 1.517 GHz signal needed in a Rb85 D1 line atomic clock based on CPT interrogation technique. Unlike frequency synthesis techniques currently used in atomic clocks and build around power consuming frequency multipliers and Digital Direct Synthesis (DDS) circuits, the proposed frequency synthesizer is build around an ultra low-noise LC-VCO for direct RF signal generation, which is PLL locked to a 10 MHz TXCO reference. The PLL includes a multi-modulus divider controlled by a 30-bit, 3rd order Sigma-Delta modulator, allowing a frequency tuning accuracy of 0.1 Hz (at 1 kHz bandwidth). The targeted performances are an overall power consumption of 20 mW, and an output phase noise of max –100 dBc/Hz within the 100 kHz PLL bandwidth. Except for the Sigma-Delta modulator implemented in FPGA, the complete frequency synthesizer has been fabricated into a CMOS 0.18 im test chip and is currently under characterization. Special techniques for noise reduction have been used for the 1.5 GHz VCO, leading to a measured phase noise of only -108 dBc/Hz at 100 kHz from the carrier, for a power consumption of 6 mW. The performance of the whole PLL, including the Sigma-Delta modulator, will be presented in the full paper version.