Halder, S; Gustat, H; Scheytt, C
IHP Microelectronics

In the last few decades the communication bandwidth has evolved with an enormous speed and the requirement of high-speed data converters is directly dictated by that. The direct digital synthesis (DDS) technique becomes more and more popular in the mobile communication arena due to the simple control procedure compared to an analog domain phase locked loop (PLL) based signal synthesis. The front end D/A converter (DAC) is a critical component in those systems. IHP is already working on a broadband DAC for ESA (12 bit, 1.5 GS/s, bandwidth <1GHz) as a subcontractor of Kayser-Threde. Beside that, medium resolution (4-8 Bits) DACs with sampling rate up to 20 GHz are going to be used in high speed data links e.g. optical, radar or satellite communication systems.

In this paper, the design of a 20GHz 8-bit modified segmented current steering DAC is presented, based on measured results of a 4-bit DAC [1]. The main improvement over previous current-steering DACs is done in the 4-bit LSB sub-DAC design. Unlike the conventional segmented current steering DAC, this LSB sub-DAC is implemented with an R-2R ladder network. This enables to have the same output current for all of the unit current cells in the LSB and MSB sub-DACs. Hence it provides better matching among the current cells as well as improved and better predictable switching dynamics.

In the context of a multi-GHz unary weighted DAC design the thermometer decoder comes as the bottleneck. A new approach based on OR/NOR DFF [2] is used for an HBT ROM to implement the 4-bit binary to thermometer decoder.

The DAC is implemented in a 0.25 ¦Ìm SiGe SG25H1 BiCMOS technology. The minimum emitter size of the HBT is 0.21x0.84 ¦Ìm2 and the fT, fMAX are both 190GHz. This technology provides three thin metal layers and two thick metal layers for the RF inductors and low loss microstrip lines. The CMOS part is identical to other IHP technologies which currently are under space qualification.

In the design of the 8-bit DAC the long clock and outputs lines are implemented with on-chip 50¦¸ microstrip lines. The full DAC test chip has an area of 6mm2. For the realistic simulation results the distributed p-model of the long interconnect lines is already included.

In simulation this 8-bit DAC shows output resolution bandwidth of 9GHz at the conversion rate of 20GHz. With the 9GHz full scale sinusoidal input is shows a THD of 48.9 dBc, which corresponds to 7.83 effective number of bits. Total power dissipation of the DAC at 20GHz conversion rate is 2.5W.

The 4-bit bit LSB sub-DAC has already been implemented and measured in IHP's 0.25µm SG25H1 technology. The DAC was implemented with a modified resistive ladder network. The die area with pads was 1.87mm2. The characterization of this 4-bit DAC was performed in the time domain [2]. It shows an INL and DNL of 0.49LSB and 0.57LSB respectively. Due to limits of the bit-pattern generator, the 4-bit DAC test data rate was ¡Ü3.3GHz. The dynamic performance was extrapolated from measurements at this data rate. The 4-b-DAC showed 3.85GHz of output bandwidth. It was functional up to 30GHz of conversion rate with a power dissipation of 455mW, resulting in a figure of merit (FOM) of 0.95pJ. According to the authors knowledge this 4-bit DAC shows the second highest conversion rate in Si/SiGe technology.

[1]S. Halder, H. Gustat, " A 30 GS/s 4-Bit Binary Weighted DAC in SiGe BiCMOS Technology ", Proc. BCTM, pp 46-49, 2007
[2] H. Gustat, J. Borngraber, "NOR/OR register based ECL circuits for maximum data rate", Proc. BCTM, pp 90-93,2005.