CMOS Technologies for RF Applications in Harsh Environment
Raskin, J.P; El Kaamouchi, M; Emam, M; Roda Neve, C; Janvier-Vanhoenacker, D
Université catholique de Louvain

The new communication systems are very demanding; high frequency, high degree of integration, low power consumption, and they have to present good performance even under harsh environment.

The integrability and power consumption reduction of the digital part will further improve with the continued downscaling of technologies. The bottleneck for further advancement is the analog front-end. Present-day transceivers often consist of a three or four chip-set solution combined with several external components. A reduction of the external components is essential to obtain a lower cost, power consumption and weight, but it will lead to a fundamental change in the design of analog front-end architectures. The analog front-end requires a high performance technology, like GaAs or silicon bipolar, with devices that can easily achieve operating frequencies in the GHz range. For the digital signal processor a small device feature size is essential for the implementation of complex algorithms. Therefore, it appears that only the best submicron CMOS technologies allow for a feasible and cost-effective integration of the communication systems.
This last decade Silicon-on-Insulator (SOI) MOSFET technology has demonstrated its potentialities for high frequency and harsh environments (high temperature, radiations) commercial applications. Indeed, thanks to the buried oxide layer underneath the thin silicon channel, SOI MOSFETs do not suffer from the leakage current through the well junctions which becomes very large at high temperature and from the Single-Event-Upset (SEU) under radiation contrary to the classical bulk silicon MOS technology [1].

In that paper, we present the performance of low-power and high-temperature LNA (low noise amplifier) and RF switches designed in SOI CMOS technology and operating at high temperature as well as an analysis concerning the interest of high resistivity SOI substrates for fully integrated mixed-mode communication systems.

The design of microwave circuits for high temperature application is made at a point where important parameters of the MOSFET show zero or very small variation with temperature. The Zero-Temperature-Coefficient of gm (ZTCgm) has been identified experimentally for SOI MOSFET’s [2]: there typically exists a gate-voltage (VGS) value at which transistor transconductance does not change with temperature.
The devices and circuits have been fabricated on a partially depleted 130-nm SOI CMOS process provided by ST-Microelectronics, which is a single poly CMOS process using SOI UNIBOND wafers with a high resistivity (>1 kOhms.cm). This process features 2-nm gate oxide, Cobalt silicide on junctions and polysilicon gates and lines, with six copper metal levels and an additional top metal layer in Aluminum. The nMOS transistors exhibit fT and fMAX of 89 GHz and 125 GHz, respectively, for VDS=1.2 V, at room temperature.
A cascode inductive source degeneration topology was adopted for the design of a LNA at 2.4 GHz. On-wafer measurements were performed at ZTCgm bias point (VDS=0.6 V and VGS=0.42 V for each transistor), over the temperature range from 25 to 250°C. The measured S21 and S11 of the LNA show a very small degradation versus temperature. There is however an increase of 67% of the NF at 2.4 GHz, mainly due to resistive losses in the lines.
The complete integration of RF communication systems requires the use of a single antenna for both transmission and reception stages. This can be achieved by implementing a proper RF antenna switch. SOI technology offers the opportunity to design integrated circuits on high resistivity substrates leading to reduced losses as well as improved substrate insulation [3], without losing latchup immunity. Built RF switches present an insertion loss lower than 1 dB and isolation better than 40 dB at 2.4 GHz and a negligible degradation of their performance up to 200°C.
It has been demonstrated that high resistivity silicon substrates suffer from surface effects and resistivity degradation near the insulating oxide. Indeed, charges within the oxide attract free carriers near the substrate surface, reducing the effective resistivity seen by coplanar devices, increasing the substrate losses and the crosstalk between integrated circuits. We have recently shown that parasitic surface conduction can be reduced or even suppressed if the silicon substrate is passivated before oxidation with a trap-rich, highly resistive layer [4].

Based on several built and tested RFIC, SOI CMOS technology demonstrated its potentialities to fulfill the specifications of advanced communication systems operating under harsh environment such as high temperature and space radiation.

[1] J.-P. Colinge, Silicon-on-Insulator Technology: Material to VLSI, Springer-Verlag, 2004.
[2] D. S. Jeon et al., IEEE TED, 1991.
[3] J.-P. Raskin et al., IEEE TED, 1997.
[4] D. Lederer et al., IEEE EDL, 2005.