First Test Results of a Single Chip SiGe Fractional-N PLL for Converter and Local Oscillators at 10 and 18 GHz
Lenz, R.¹; Heyer, H.-V.¹; Follmann, R.²; Koether, D.²; Schmalz, K.³; Herzel, F.³; Winkler, W.³; Nilsson, J.⁴; Folio, B.⁵; Glass, B.⁵; Piironen, P.^5
1Kayser-Threde GmbH; ²IMST GmbH; ³IHP GmbH; ⁴SAAP Space; ⁵ESTEC

After a study of the Local Oscillator (LO) architecture, the system parameters and specifications of the PLL sub-circuits have been derived. The first PLL was realized as a two-chip solution (BiCMOS part and CMOS part). Measurement results of the two-chip PLL contributed to the design of the first one-chip PLL. This single chip PLL was manufactured using the IHP SiGe 0.25µm technology SGB25V and contains the VCO, Phase Frequency Detector (PFD), Charge Pump (CP), modulus divider, main divider and the fractional-N CMOS logic on one die. The LO chip offers the possibility to use both the internal or an external VCO.

The latest measurements show that the analog input reference has an excellent phase noise behaviour which is extremely important for the quality of the output signal. The phase noise of the complete divider chain (prescaler, dual modulus and main counter) is below -150 dBc/Hz. The free running 10 GHz VCO phase noise is within the target values and the temperature behaviour seems to be less critical than previously anticipated. The linearity of the PFD/CP component was measured. The LO test results will be covered in more detail in this paper.

The next single chip 10 GHz LO manufacturing is scheduled for May 2008. The charge pump design will be modified to improve linearity and phase noise. An improved divider architecture will increase the performance of the main counter and enhance the timing of the interface between the sub-circuits.

Moreover, the radiation tolerance of the used SiGe technology (SGB25V) has been analysed by irradiating representative test structures like bipolar transistors or simple logic circuits (SEE and TID verifications). The irradiation tests of the LO chip will be performed later this year.

The final commercial product will be a packaged MMIC containing the single chip LO. This MMIC will be subject to ESCC qualification tests.

Funding for these activities was made available by ESA (TRP and ARTES programmes) and DLR.